A DRAM is capable of high-speed read (Read)/write (Write) operations. However, the DRAM is a volatile memory and hence is in need of refresh (Refresh) operations for data retention. Consequently, the DRAM suffers a problem that the data holding current is increased. The reduction of the data holding current in the DRAM during the standby time thereof is demanded.
A flash memory (Electrically Erasable and Programmable ROM or EEPROM) or a phase change memory, as a non-volatile memory, capable of high integration density, is not in need of power supply for data retention, however, suffers the problem that it is low in its write speed and in rewrite withstand characteristic.
In Patent Document 1, there is disclosed a memory in which a DRAM chip, an SRAM (static random access memory) chip, or a DRAM chip and a FLASH memory, are mounted in one seal package to increase the storage capacity and to decrease the data holding current. In Patent Document 2, there is disclosed a memory apparatus employing a volatile memory (SDRAM) and a non-volatile memory (FLASH memory), in which the non-volatile memory may be accessed from a host to provide for improved controllability from the host. In Patent Document 3, there is disclosed a configuration comprising a volatile first memory and a non-volatile memory cell (MRAM) connected to the first memory cell. In this configuration, data may be written in the first memory cell or the non-volatile memory cell, whilst data from the first memory cell or the non-volatile memory cell may be transferred to the non-volatile memory cell or the first memory cell.    [Patent Document 1]
JP Patent Kokai Publication No. JP-P2003-6041A    [Patent Document 2]
JP Patent Kokai Publication No. JP-P2003-91463A    [Patent Document 3]
JP Patent Kokai Publication No. JP-P2004-39229A